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Physical optimization and CTS at the same time
Up to 20% increase in chip speed
Faster time to market with fewer iterations to RTL
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Smaller clock skew, insertion delay and area
Up to 40% reduction in clock power
Faster time to market for designs with complex clocks
"Azuro's PowerCentric™ truly is a fresh approach to CTS, and enables us to deliver silicon to market faster and with even lower power consumption than before."
— Steve Padnos, Methodology Architect for Atheros
"...Azuro provided Broadcom with design automation tools that assisted in reducing the active power consumption of our BCM2702 mobile multimedia processor."
— Steve Barlow, Sr Director Engineering, Broadcom
"...Low power is a key driver for CSR. PowerCentric™ fits seamlessly into our design flow and has enabled us to achieve significant reductions in the digital power consumption of our chips."
— James Collier, Co-founder and CTO, CSR
"Our customers' power requirements push the limits of cooling and power supply, so reducing power consumption is a critical issue for these applications. We adopted PowerCentric™ in order to maintain our leadership in delivering low power solutions to our customers."
— Ravi Selvaraj, Vice President of Product Development, Ikanos
"PowerCentric™ gives us the ability to implement superior clock trees inside our existing physical framework of EDA tools."
— David Dumoulin, Director of Engineering at NVIDIA
"In our evalution, PowerCentric™ delivered 15 to 25 percent reduction in power consumption compared to our existing implementation with minimum impact on design size or performance..."
— Atsushi Watanabe, Vice President Design Solutions at TAEC
"Azuro's PowerCentric™ tool delivers significant power savings, and improves clock timing by reducing clock skew and insertion delay."
— S. T. Juang, Senior Director of Design Infrastructure Marketing for TSMC
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