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“ARC continuously strives to offer
best-in-class configurable solutions that fit the stringent needs of
customers designing SoCs for power sensitive applications. By
leveraging Azuro’s PowerCentric low power methodology, licensees can
further reduce power consumption of ARC’s configurable subsystems and
processors by more than 20% without impacting processor footprint.”
Peter Hutton
Senior Vice President of Engineering
ARC International |
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“Clock tree synthesis is a
critical step in the design flow which the EDA industry has
under-invested in for some time now. Azuro's PowerCentric truly is a
fresh approach to CTS, and enables us to deliver silicon to market
faster and with even lower power consumption than before.”
“Using Azuro’s
PowerCentric, Atheros has been able to improve the quality of our clock
trees. This increased ability to manage clock distribution has
contributed to the low power dissipation of our mobile and client
products.”
Steve
Padnos
Methodology Architect
Atheros
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“Power dissipation has
become increasingly important to the semiconductor industry as
consumers demand ever more talk time, play time, and functionality in
their next-generation mobile phones and portable devices. Meeting power
requirements is one of the biggest challenges facing chip design teams
today. Without effective clock gating, most of the active power in a
typical digital logic block is consumed by the clock and registers.
Azuro provided Broadcom with design automation tools that assisted in
reducing the active power consumption of our BCM2702 mobile multimedia
processor.”
Steve
Barlow
Senior Director of Engineering
Mobile Multimedia Products
Broadcom
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“Low power is a key driver
for CSR. PowerCentric fits seamlessly into our design flow and has
enabled us to achieve significant reductions in the digital power
consumption of our chips.”
James
Collier
Co-founder and Chief Technology Officer
CSR
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“Our customers’ power
requirements push the limits of cooling and power supply, so reducing
power consumption is a critical issue for these applications. We
adopted PowerCentric in order to maintain our leadership in delivering
low power solutions to our customers.”
Ravi Selvaraj
Vice President of Product Development
Ikanos Communications
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"For NVIDIA,
we must deliver unmatched features and performance in
our graphics, multi-media communication processors and application
processors while meeting tight power budgets, performance and area
constraints. Consequently, our designs contain extremely complex clock
trees with multiple branches at the block level that also needs to be
balanced for min./max. corners. PowerCentric gives us the ability to
implement superior clock trees inside our existing physical framework
of EDA tools.”
David
Dumoulin
Director of Engineering
NVIDIA
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"PowerCentric
was able to greatly reduce dynamic clock power by
finding many more clock-gating opportunities and building much more
efficient clock trees. Azuro’s results are especially impressive
because they are more efficient across the board. The low-power result
also achieved a better clock skew, a shorter insertion delay, and
reduced total buffer area.”
Nobuyuki
Nishiguchi
Vice President of the Design Methodology Group STARC
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“Power has become one of
the critical drivers for TAEC customers. In our evaluation,
PowerCentric delivered 15 to 25 percent reduction in power consumption
compared to our existing implementation with minimum impact on design
size or performance. Since many of our customers have designs that sit
on the cusp of a power/performance envelope, this power reduction could
make possible an array of low-cost, package solutions. “PowerCentric
integrates smoothly into our low-power design flow as an alternative to
our current clock tree synthesis capability. In addition to its power
reduction benefits, the product also offers extensive features to
analyze our clock trees and power dissipation, which we believe will
significantly enhance the productivity of our engineers on designs
containing complex clock topologies.”
Atsushi
Watanabe
Vice President Design Solutions
TAEC
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“The increase in design
complexity and the demand for low power highlights clock implementation
as an emerging bottleneck for design performance and designer
productivity. Azuro’s PowerCentric tool delivers significant power
savings, and improves clock timing by reducing clock skew and insertion
delay.”
S.T.
Juang
Senior Director of Design Infrastructure Marketing
TSMC
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