Media Coverage

July 7, 2010	TSMC Adopts Azuro's Rubix for Embedded CPU Hardening EDACafé
June 16, 2010	Azuro enhances clock tree synthesis tool EE Times
January 19, 2010	Azuro reports growth in 2009 EE Times
October 5, 2009	Azuro appears on EE Times list of emerging startups version 9.0 EE Times
July 28, 2009	IEEE 1801™ UPF Solutions Guide Accellera Publication
July 22, 2009	TSMC Extends Design Methodology Leadership to 28nm With Reference Flow 10.0 TSMC Press Release
June 9, 2009	Skew This! Azuro Touts Clock Concurrent Optimization for Aggressive Nodes IC Design and Verification Journal
May 25, 2009	Peggy Aycinena on Advanced CTS – Azuro's Campaign EDACafé
May 12, 2009	Physical Synthesis is Broken – Why Clocks Are Crippling Migration to 45nm and Below Chip Design Magazine
May 12, 2009	Low Power CTS Tool Integrated SignOff Flow Chip Design Magazine
April 21, 2009	TSMC sign-off flows and reference designs: helping customers and treading on toes? EDN
April 21, 2009	Azuro Included in TSMC's Standard Signoff Flow EE Times
April 7, 2009	Azuro discusses Rubix tool Electronicstalk
March 5, 2009	Azuro dévoile un outil d'optimisation double des horloges d'une puce Electronique International
March 2009	Hot-Off-The-Press: Azuro's Rubix Clock Concurrent Optimization Tool Chip Design
February 26, 2009	Azuro Intros New Clock Concurrent Optimization Tool TMCNet
February 25, 2009	Azuro offers up to 30 percent clock frequency bonus with new clock optimization tool EDN
February 2, 2009	EE Times updates list of emerging startups to version 8.0 EE Times
September 23, 2008	Viewpoint: Innovation is being delivered by plug-and-play start-up solutions EDA DesignLine
August 2008	Interview with Paul Cunningham, CEO of Azuro SCDsource
June 2008	Video interview at DAC with Paul Cunningham, CEO of Azuro EDACafé
June 24, 2008	Optimize IC Power by Understanding Circuit Activity SCDsource
June 9, 2008	Low Power is Now a High Priority SOCcentral
June 3, 2008	TSMC Rolls 40-nm Design Flow EE Times
January 31, 2008	The Hidden Impact of Circuit Activity on Power Chip Design
November 9, 2007	STARC Adopts Azuro's Clock-Tree Synthesis EE Times
March 2007	Azuro's CEO Paul Cunningham named one of Business Week's Best Young Entrepreneurs in Tech Business Week
Oct 5, 2006	Si2 Announces Formation of Low Power Coalition Si2
July 24, 2006	Using Statistical Activity for Power Estimation EE Times
July 5, 2006	Power reduction tool extends to 65-nm EE Times
July 5, 2006	Azuro Cuts Power in 65nm Designs Electronic News
June 1, 2006	Burn Baby, Burn Electronic Business
January 5, 2006	Clock-tree Design Startup Raises $9 Million EE Times
December 12, 2005	The Hot 100 Products of 2005 EDN Magazine
Nov/Dec 2005	Power Drivers and Power Metrics Chip Designer
June 13, 2005	Who to Watch at DAC EE Times
June 13, 2005	Whizzy New Tools Dangled at DAC EE Times
June 6, 2005	Azuro Unveils Low Power Clock Implementation SOCcentral
May 17, 2005	Power-savvy Tool Replaces Clock-tree Synthesis EDN
May 16, 2005	Startup Targets Power Problems in Wireless IC Design EE Times
May 16, 2005	Azuro Targets Clock Tree Power Electronics Weekly
July 2004	Radar Scope Semiconductor Times (321 KB PDF file)