« back to Press releases main

Apache Design Solutions and Azuro Present Technical Webinar
on Low Power Design and Analysis

On-line Webinar to Focus on Power Reduction and Leakage Management

MOUNTAIN VIEW, CA– June 1, 2006 – Apache Design Solutions, the technology leader in power and noise integrity solutions for SoC designs, and Azuro, Inc., a provider of innovative electronic design automation (EDA) tools that significantly reduce the power consumption of digital semiconductor chips, are offering a webinar focused on power reduction and leakage management for silicon sign-off. The webinar titled “Power Reduction: Magic or Methodology” will be hosted live on June 8, 2006 at 9:00am Pacific Daylight Time.

As designs move beyond 90nm, "power management" becomes the key design challenge faced by the engineers. In order to achieve reliable silicon sign-off, the design teams are exploring effective methods for reducing and managing switching and leakage power. In this informative webinar, Apache and Azuro will each detail their advanced low power solutions and how these solutions will reduce power consumption and increase accuracy of silicon sign-off. Specifically, the webinar will discuss

• Dynamic power, what role the clock tree plays, and why it's so critical to manage clock power during clock tree synthesis;
• Leakage power, how it impacts the overall power, and design and analysis techniques to control leakage;
• Important differences between peak power and average power analysis for EDA design flows;
• Sign-off analysis and the impact of dynamic voltage drop on timing and jitter.

Register

About Apache Design Solutions
Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design, such as power, signal, package / system IO, substrate, and temperature, Apache's silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor neutral platform enables designers to adopt any industry's standard physical design flow and is certified by TSMC's 5.0 and 6.0 Reference Flow (NYSE: TSM). Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies. For more information, visit www.apache-da.com.

About Azuro
Azuro, Inc. is a provider of innovative electronic design automation (EDA) solutions that significantly reduce the power consumption of digital semiconductor chips. Founded in 2002, the privately held company is headquartered in Mountain View, Calif., with a development center in Cambridge, UK. For further information, visit www.azuro.com or call (650) 237-3500.

# # #

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Contacts:

Azuro – Jennifer Bilsey, (650) 237-3505, jen@azuro.com

Cayenne Communication – Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com