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Azuro Enables PowerCentric for 65nm

Variability-aware Low Power Clock Implementation Solution Offers 15-25%
Additional Power Savings

MOUNTAIN VIEW, CA– July 5, 2006 – Azuro, Inc., a provider of power reduction solutions for digital designs, today announced version 3 of its PowerCentric low power clock implementation solution. PowerCentric 3.0 extends the company’s unique 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below. Key features for this new release include:

• Variability-aware low power clock buffering and clock gating;
• Global skew driven optimization with concurrent multi-corner constraints;
• Automatic useful skew insertion for setup and hold timing closure across multiple modes and corners;
• Clock tree buffering and gating across multiple voltage islands;
• Powerful GUI with advanced variability-aware clock QoR analysis capabilities.

“Clock implementation is becoming increasingly critical at nanometer geometries," said Ashutosh Mauskar, Vice President of Product Marketing for Azuro. "If performance and gate area are all that matter, then clock implementation is a well contained problem. But if power, routability, and variability are important, then clock implementation becomes a critical part of the design flow. Using PowerCentric, Azuro’s customers are able to manage all these variables during clock implementation and achieve 15 to 25% power reduction without any impact on the size or performance of their chips.”

PowerCentric operates as a complete replacement for traditional clock tree synthesis (CTS) in digital ASIC design flows. By unifying clock gate synthesis and clock tree buffering into a single physically-aware optimization engine operating at the placed-gates level in the design flow, PowerCentric is able to insert up to 3x more clock gating than current low power industry design flows.

Azuro will demonstrate PowerCentric 3.0 at the 43rd Design Automation Conference (DAC) July 24-27, 2006 at the Moscone Convention Center in San Francisco, CA in booth #1928.

About Azuro
Azuro, Inc. is a provider of innovative electronic design automation (EDA) solutions that significantly reduce the power consumption of digital semiconductor chips. Founded in 2002, the privately held company is headquartered in Mountain View, Calif., with a development center in Cambridge, UK. For further information, visit http://www.azuro.com/ or call (650) 237-3500.

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Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Contacts:

Azuro – Jennifer Bilsey, (650) 237-3505, jen@azuro.com

Cayenne Communication – Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com