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STARC Adopts Azuro's Clock Tree Synthesis Solution for Ultra Low Power Methodology

PowerCentric Reduces Dynamic Power by 20% in the Latest STARCAD-CEL Reference Flow for Major Japanese Semiconductor Companies

SANTA CLARA, CA–November 9, 2007–Azuro, Inc. the provider of advanced clock implementation tools for nanometer (nm) chip design, today announced that the Semiconductor Technology Academic Research Center (STARC) has adopted Azuro’s PowerCentric™ clock tree synthesis and optimization solution for its Ultra Low Power STARCAD-CEL V1.5 reference methodology. STARC is an influential consortium of major Japanese semiconductor companies that is leading the way in developing advanced IC design methodologies for silicon process technologies down to 32nm. By adding PowerCentric to its Ultra Low Power flow, STARC was able to reduce the total dynamic power consumption by 20%.

“PowerCentric was able to greatly reduce dynamic clock power by finding many more clock-gating opportunities and building much more efficient clock trees,” said Nobuyuki Nishiguchi, vice president of the Design Methodology Group at STARC. “Azuro’s results are especially impressive because they are more efficient across the board. The low-power result also achieved a better clock skew, a shorter insertion delay, and reduced total buffer area.”

PowerCentric achieves better clock tree timing by unifying the traditionally separate steps of clock-gating and clock-buffering into a single step. It also reduces the dynamic clock power by optimizing existing clock-gates and by synthesizing new clock-gates. The clock optimization is based on actual or vectorless activity data, and is done in context of the placed netlist. This allows PowerCentric to manage the critical optimization trade-offs between power, speed and routability concurrently across multiple modes and corners.

“We are seeing significant interest for our PowerCentric solution in Japan,” said Paul Cunningham, co-founder and chief executive officer of Azuro. “I’m delighted to be working with STARC to accelerate the deployment of PowerCentric to STARC’s member companies.”

About Azuro
Azuro, Inc. is a provider of advanced clock implementation tools for nanometer chip design. Azuro's PowerCentric™ is a complete solution for clock tree synthesis (CTS) and post-CTS optimization. Its patented technology reduces the power consumption of digital ICs by 20%, improves designer productivity, and accelerates the time-to-market for SOCs with complex clocks. Founded in 2002, the privately held company is headquartered in Santa Clara, California, with R&D offices in Cambridge, UK. For further information, visit http://www.azuro.com or call (408) 970-8200.

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Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Contacts:

Azuro – Jennifer Bilsey, (408) 970-8205, jen@azuro.com

Cayenne Communication – Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com