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Atheros Delivers Advanced Bluetooth 2.1 + EDR Silicon Using Azuro's PowerCentric

PowerCentric generates superior quality clock trees and reduces post-CTS design flow iterations for Atheros

SANTA CLARA, CA – January 28, 2008 – Azuro, Inc. the provider of advanced clock implementation tools for nanometer chip design, today announced that Atheros Communications, Inc. (NASDAQ:ATHR), a leading developer of advanced wireless solutions, has successfully produced working silicon on the AR3011 single chip Bluetooth 2.1 + EDR design for high-performance mobile and embedded wireless products using Azuro’s PowerCentric™.

Atheros’ design was already aggressively clock gated using front-end RTL synthesis tools in addition to containing multiple levels of hand-crafted clock gating logic. By utilizing PowerCentric, Atheros was able to generate superior quality clock trees, reduce post-CTS design flow iterations, and achieve significant reductions in total chip power consumption without any impact on chip size or performance.

“Clock tree synthesis is a critical step in the design flow which the EDA industry has under-invested in for some time now,” said Steve Padnos, Methodology Architect for Atheros. “Azuro's PowerCentric truly is a fresh approach to CTS, and enables us to deliver silicon to market faster and with even lower power consumption than before.”

Azuro's PowerCentric is a complete replacement for CTS and post-CTS optimization. Unlike traditional CTS solutions, PowerCentric's unique multi-objective algorithm directly considers power, congestion, and timing across multiple modes and corners during the clock tree buffering process. By combining this multi-objective algorithm with advanced logic path timing and placement optimization methods, PowerCentric is able to deliver ultra-low power clock structures without impacting design speed or area, even for the most complex SoC designs.

“Ultra-complex, ultra-low power clock trees are very common in mobile device markets," said Paul Cunningham, co-founder and chief executive officer for Azuro. “Whereas a previous version of this Atheros chip required multiple iterations between CTS and timing analysis, this was not the case using PowerCentric. This success with Atheros is a great example of how Azuro’s multi-objective clock solution helps its users deliver the best silicon to market, and do it quickly.”

About Azuro
Azuro, Inc. is a provider of advanced clock implementation tools for nanometer chip design. Azuro’s unique technology delivers significant power, speed and time-to-market benefits and is being used by leading semiconductor companies around the globe to design cellular modem chips, multimedia chips, network switches, graphics chips, Bluetooth and WiFi chips, embedded processors, PC chipsets, and many other mobile and line powered devices. Founded in 2002, the privately held company is headquartered in Santa Clara, California, with R&D offices in Cambridge, UK. For further information, visit http://www.azuro.com or call (408) 970-8200.

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Azuro, PowerCentric, and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Contacts:

Azuro – Jennifer Bilsey, (408) 970-8205, jen@azuro.com

Cayenne Communication – Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com