PowerCentric
PowerCentric™ is a clock tree synthesis (CTS) and post-CTS optimization tool that reduces clock power by up to 40%, reduces insertion delays by up to 20%, and accelerates time to market for designs with complex clocks. PowerCentric fits seamlessly into a design flow after physical optimization and before routing, using industry standard file formats as its inputs and outputs. The product has been used on over 50 tapeouts from 180nm to 40nm and is part of TSMC's official Reference Flow and also TSMC's Integrated Sign-off Flow.

Traditional clock tree synthesis tools build balanced clock networks using top-down or bottom-up buffering methods. These methods are unable to consider the totality of a clock network as part of their decision making process, and therefore build inefficient clock structures. The more clock muxes, clock generators, and clock gates there are in a design the more inefficient traditional bottom-up or top-down methods become.
PowerCentric exploits a unique "globalized" buffering technology which intelligently determines the most efficient places to insert buffers to ensure that a clock network is balanced. This determination is based on global perspective of the entire clock network including clock muxes, clock generators, and clock gates. Clock networks built using PowerCentric are smaller, lower power, and have lower insertion delays than clock networks built using traditional bottom-up or top-down only methods. The more complex a clock network the bigger the benefits of using PowerCentric become.
PowerCentric augments its unique globalized buffering technology with a proprietary set of timing, activity, and congestion aware algorithms which extensively reconfigure clock gating topologies and perform timing optimization on clock gate enable logic. These algorithms also synthesize additional, entirely new, clock gating into a design above and beyond clock gating inserted during RTL synthesis. The tight coupling of aggressive clock gate optimization and globalized clock buffering results in a dramatic reduction in clock power when using PowerCentric.
In addition to improving clock power and insertion delay, PowerCentric also increases productivity and accelerates time to market on designs with very complex clocks that require complex skew group configurations to ensure that they are balanced correctly. This is in part due to the highly flexible nature of PowerCentric's globalized buffering technology which seamlessly supports overlapping multi-parent skew groups, but also due to PowerCentric's powerful interactive visualization capabilities and ultra-fast virtual delay based "trial CTS" which streamline clock tree debugging and configuration on complex designs.
Key Benefits
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Up to 40% reduction in clock power |
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Up to 20% reduction in insertion delay |
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Accelerated time to market on designs with complex clocks |
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Key Features
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Clock tree buffering |
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Advanced gate level clock gate insertion |
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Clock gate enable timing optimization |
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Timing Analysis |
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Power Analysis |
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Global routing |
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Powerful GUI |
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