PowerCentric

PowerCentric™ is a clock tree synthesis (CTS) and post-CTS optimization tool that reduces clock power by up to 40%, reduces insertion delays by up to 20%, and accelerates time to market for designs with complex clocks. PowerCentric fits seamlessly into a design flow after physical optimization and before routing, using industry standard file formats as its inputs and outputs. The product has been used on over 50 tapeouts from 180nm to 40nm and is part of TSMC's official Reference Flow and also TSMC's Integrated Sign-off Flow.

Traditional clock tree synthesis tools build balanced clock networks using top-down or bottom-up buffering methods. These methods are unable to consider the totality of a clock network as part of their decision making process, and therefore build inefficient clock structures. The more clock muxes, clock generators, and clock gates there are in a design the more inefficient traditional bottom-up or top-down methods become.

PowerCentric exploits a unique "globalized" buffering technology which intelligently determines the most efficient places to insert buffers to ensure that a clock network is balanced. This determination is based on global perspective of the entire clock network including clock muxes, clock generators, and clock gates. Clock networks built using PowerCentric are smaller, lower power, and have lower insertion delays than clock networks built using traditional bottom-up or top-down only methods. The more complex a clock network the bigger the benefits of using PowerCentric become.

PowerCentric augments its unique globalized buffering technology with a proprietary set of timing, activity, and congestion aware algorithms which extensively reconfigure clock gating topologies and perform timing optimization on clock gate enable logic. These algorithms also synthesize additional, entirely new, clock gating into a design above and beyond clock gating inserted during RTL synthesis. The tight coupling of aggressive clock gate optimization and globalized clock buffering results in a dramatic reduction in clock power when using PowerCentric.

In addition to improving clock power and insertion delay, PowerCentric also increases productivity and accelerates time to market on designs with very complex clocks that require complex skew group configurations to ensure that they are balanced correctly. This is in part due to the highly flexible nature of PowerCentric's globalized buffering technology which seamlessly supports overlapping multi-parent skew groups, but also due to PowerCentric's powerful interactive visualization capabilities and ultra-fast virtual delay based "trial CTS" which streamline clock tree debugging and configuration on complex designs.

Key Benefits

Up to 40% reduction in clock power	Unique globalized approach to clock buffering Advanced clock gate topology restructuring Additional clock gate insertion based on symbolic analysis of logic cones driving flip-flop inputs
Up to 20% reduction in insertion delay	Unique globalized approach to clock buffering Eliminate insertion delay bottlenecks by reconfiguring clock gating topology
Accelerated time to market on designs with complex clocks	Drastically reduces manual effort required to configure and balance complex clocks Early detection and correction of balancing problems with ultra-fast virtual delay based "trial CTS" Powerful GUI with extensive interactive clock tree visualization and debugging capabilities

Key Features

Clock tree buffering	Seamless ability to handle extensive clock re-convergence and hundreds of skew groups Supports complex re-convergent clock networks across multiple voltage domains Ultra fast runtime virtual delay based "trial CTS" capability Correct timing for mixed rising and falling edge triggered flops Supports overlapping multi-parent skew groups Supports multi-corner skew targets Supports complex clock tree routing rules
Advanced gate level clock gate insertion	Identifies additional clock gate enable conditions at the gate level beyond frontend clock gating tools Clock gate optimization driven by accurate STA timing of enable conditions Placement, congestion, and activity aware
Clock gate enable timing optimization	Congestion and timing aware global placement and legalization Cell sizing Timing-driven high fanout net synthesis All algorithms operate seamlessly across multiple voltage regions
Timing Analysis	Industry standard static timing analysis based on SDC constraints Multiple setup and hold corners OCV derates and CPPR Multiple modes
Power Analysis	Full chip dynamic and leakage power analysis VCD, SAIF, TCF import Vectorless statistical average-case activity estimation
Global routing	Advanced statistical track and metal layer assignment Supports shielding, variable spacing, and load-based routing rules Route guide export for detailed routing
Powerful GUI	Skew, logical, and physical clock tree views Schematic view Full cross-probing between all views Highlight based on skew, slack, slew, activity, congestion, and other metrics Fully Tcl scriptable design environment and data model