CTS is traditionally thought of as just a step in the design flow where buffer trees are inserted onto clock nets to meet a given slew and skew target. However, CTS can also be viewed as the step in the design flow which transitions the timing of a design from an abstracted "ideal clocks" method, as used during RTL design and synthesis, to a true "propagated clocks" method, as used during final layout and timing sign-off. When viewed in this way, the purpose of a CTS tool is to ensure that propagated clocks timing post-CTS correlates reasonably well with ideal clocks timing pre-CTS.

Traditionally, designers have assumed that if their skew constraint is tight enough, the transition from ideal clocks timing to propagated clocks timing can be made effectively painless. Unfortunately, this assumption no longer holds for today's complex SoCs developed at nanometer geometries. In particular complex muxed and generated clock configurations, aggressive clock gating, on-chip variation, multi-mode, and multi-corner considerations all fundamentally impact propagated clocks timing in ways that cannot easily be represented using ideal clocks timing. As a result building clocks just to meet a slew and skew target is no longer sufficient to reliably bridge the gap between pre and post-CTS stages in the design flow.

Effective clock design at nanometer geometries requires a fundamental rethink of the role of CTS in the design flow. A CTS tool for nanometer design must not just worry about meeting slew and skew targets or other clock tree balancing constraints – it must directly consider the underlying objectives which matter to the designer, such as timing and power across different modes and corners, design area, utilization, and congestion. In essence the primary goal of CTS in the nanometer era should be to manage the transition across the ideal-to-propagated divide in such a way as to deliver the best quality silicon according to which objectives matter most to the designer. Meeting slew and skew targets is a means to an end and not the end in itself. Azuro refers to this new approach to clock tree synthesis as "multi-objective clock implementation".