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PowerCentric. Comprehensively addressing power, timing, and variability within one unified optimization environment.
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| Reduced power |
- Significantly less clock tree
buffer and wire capacitance
- Additional clock gating above and
below RTL clock gating
- True optimization for lowest cap x
freq not just lowest cap
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| Improved
variability management |
- Control clock skew concurrently
across multiple corners
- Concurrent multi-corner hold fixing
- Concurrent multi-corner aware
useful skew
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| Enhanced timing
closure |
- Timing aware clock gate hierarchy
restructuring
- Integrated timing optimization for
clock gate enable logic
- Multi-stage useful skew for setup
and hold with OCV derates
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| Increased
productivity |
- Reduced flow iterations between CTS
and post-CTS optimization
- Eliminate the need for complex
clock tree configuration scripts
- Understand complex clock structures
quickly with unique GUI
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