| Timing Analysis |
- Built-in static timing engine with
full SDC support
- Excellent correlation with 3rd
party sign-off tools
- Setup and hold timing analysis
- OCV derates and CPPR
|
| |
| Power Analysis |
- Full chip dynamic and leakage power
reporting
- VCD, SAIF, TCF import
- Fully vectorless statistical
average-case activity estimation
|
| |
| Variability
Analysis |
- Concurrent multi-mode timing
analysis*
- Concurrent multi-corner timing
analysis*
- Concurrent multi-mode power
analysis
- Full MSV support with CPF/UPF
roadmap*
|
| |
| Placement and
logic optimization |
- Congestion and timing aware global
placement and legalization
- Cell sizing and logic
re-structuring
- High fanout net synthesis
- Multi-corner hold fix buffer
insertion*
|
| |
| Global routing |
- Advanced statistical track and
metal layer assignment
- Wire caps estimated based on 3D
field solver
- Supports shielding, variable
spacing, and load-based routing rules
|
| |
| Clock tree
balancing |
- Global skew and useful skew** modes
- Complex clock tree routing rule
support
- Automatic balancing of complex
muxed-clock configurations
- Concurrent multi-corner skew
minimization*
- Clock tree balancing between
voltage islands*
|
| |
| Additional gate
level clock gate enable synthesis*** |
- Above and beyond front-end clock
gating
- Placement, timing, congestion, and
activity aware
|
| |
| Powerful GUI
with advanced synthesis capabilites |
- Topological and physical clock tree
views
- Full cross-probing capabilites
between all views
- Fully Tcl scriptable design
environment and data model
|
| |
| Easy
integration with mainstream EDA design flows |
- Flat and hierarchical netlist
import and export
- Compatible with formal equivalence
checkers and design-for-test tools
|
| |
*requires "Variability" option
**requires "Timing Optimization" option
***requires "Advanced Clock Gating" option |
